Program
Tentative Schedule, Subject to Change
Organizers: Zishen Wan, Chenyu Wang, Shvetank Prakash, Andy Cheng, Arya Tschand, Vijay Janapa Reddi (Harvard)
The Architecture 2.0 workshop aims to bring together researchers and practitioners exploring how AI can fundamentally transform the design, analysis, optimization, and evaluation of computer architectures and systems. We invite both work-in-progress and completed research that advances the state of the art or opens new research directions at the intersection of AI, architecture, and systems. Topics of interest include, but are not limited to:
- Computer Architecture
- AI-driven microarchitecture design, tuning, and exploration
- AI-driven chip design, hardware code generation, synthesis, and place-and-route
- Learning-based design space exploration and architectural trade-off analysis
- Processor, accelerator, and heterogeneous system design
- GPU, TPU, and accelerator architectures and kernel optimization
- Memory systems, cache hierarchies, interconnects, and storage optimization using AI
- Learning-based performance, power, energy, and reliability modeling
- Surrogate models to accelerate architectural simulation and evaluation
- AI methods for identifying architectural bottlenecks and inefficiencies
- Systems
- AI-assisted compilers, program analysis, and code generation
- Automatic kernel transformation, scheduling, and tuning
- Cross-layer co-design across compilers, runtimes, operating systems, and hardware
- AI-driven scheduling, resource management, and system-level optimization
- Intelligent runtime systems for heterogeneous and accelerator-rich platforms
- Learning-based memory management, caching, and I/O policies
We will also conduct a tutorial on QuArch and ArchEval – datasets and characterization of AI agents as computer architects. As LLM agents begin to propose architecture mechanisms, simulator configurations, accelerator mappings, and hardware–software co-design choices, the key question is no longer whether they can generate plausible artifacts, but whether they can reason like architects: analyze workloads, formulate design goals, use simulators, predict performance, satisfy hard constraints, and decide which feasible designs are worth evaluating. Using QuArch and ArchEval as a case study, the tutorial will present a benchmark methodology for measuring these capabilities across CPU cores, memory systems, ML accelerators, distributed systems, and compute-in-memory designs. We will discuss the L1/L2/L3 evaluation settings, which progressively remove prepared harnesses and simulator feedback to distinguish assisted design-space exploration from autonomous architectural judgment. The tutorial will also cover multi-simulator benchmarking, baseline-normalized scoring, trajectory analysis, and common failure modes of current agents.computer architectures and systems. We invite both work-in-progress and completed research that advances the state of the art or opens new research directions at the intersection of AI, architecture, and systems.
Organizers: Binuraj Ravindran, Rakib Al-Fahad (Intel)
Memory capacity is increasingly becoming a limiting factor for modern cloud infrastructure, in-memory databases, and AI-serving workloads, making memory compression an attractive solution for increasing effective memory capacity and improving resource utilization. This tutorial provides a practical introduction to compressed memory systems in Linux, focusing on zswap and zram, and explores how hardware accelerators such as Intel® In-Memory Analytics Accelerator (IAA) can reduce compression overhead while enabling higher workload density. Participants will learn the fundamentals of compressed memory, Linux memory-management internals, and methodologies for evaluating key metrics including compression ratio, memory savings, CPU utilization, swap latency, throughput, and tail latency. Through case studies using Redis and other memory-intensive workloads, the tutorial demonstrates how workload characteristics influence the effectiveness of memory compression and highlights the tradeoffs between capacity expansion and application performance. By combining operating-system internals, workload characterization techniques, and real-world deployment experiences, this tutorial equips researchers and practitioners with the knowledge needed to evaluate and deploy compressed memory systems in modern data-center environments.
Coffee Break
Organizers: Ben Feinberg and William Chapman (Sandia National Laboratories)
Understanding the impacts of analog nonidealities is one of the most important aspects of designing novel hardware based on analog crossbars. Ideas which can seem like straight-forward transformations can yield dramatically different susceptibility to analog errors. This tutorial will cover the use of CrossSim to simulate a range of analog nonidealities in neural networks, digital signal processing, and scientific computing applications. This tutorial will also cover how hardware models can be added to CrossSim for use beyond architecture research. In addition to covering CrossSim for conventional analog crossbar accelerators, this talk will also discuss how CrossSim can be used to design and model analog architectures based on spiking and neuromorphic concepts using the same core non-ideality simulation.
Lunch
Organizers: Dima Nikiforov, Shengjun Kris Dong, Agustin Coppari Hollmann, Loren Hung, Ailsa Sun, Yakun Sophia Shao (UC Berkeley)
This tutorial presents an open-source runtime and scheduling stack for building, tracing, and optimizing end-to-end ML and robotic workloads on heterogeneous RISC-V SoCs. The stack combines a lightweight Zephyr-RTOS ML runtime, an end to end PyTorch model compilation flow, and an orchestration layer for multi-rate real-time workloads.
First, participants will learn how to compile PyTorch models ahead-of-time into compact Zephyr ELFs with target-specific kernels, static tensor storage, persistent hart-pinned worker pools, explicit core affinity, accelerator dispatch, correctness validation, and first-class per-dispatch tracing. The runtime supports workloads running across scalar RISC-V cores, vector processors, tightly coupled memories, and custom accelerators such as systolic arrays and outer-product units.
Secondly, the tutorial addresses the full-system problem of deploying a multi-model workload under real-time constraints to heterogeneous SoCs. This section will build upon a robotics workload with perception, planning, control, and vision-language-action (VLA)-style components. We cover how to use backend choice, task fidelity, granularity, and execution frequency as control knobs, and how to assign temporal constraints and optimization targets. Additionally, we walk through how to use an ahead-of-time scheduler to build schedules that bind model operations to HW backends, and deploy these schedules to the RTOS-based runtime.
Finally, Participants will take a VLA robotic workload from PyTorch to a running, traced, schedule-driven binary that can be deployed across instruction-set simulation, software RTL simulation, FPGA-accelerated simulation with FireSim, and commercial heterogeneous silicon. The same runtime flow can be used to study accelerator integration, multicore scheduling, memory hierarchy design, hardware/software co-design, and performance analysis pre-silicon.
The tutorial also shows how runtime traces can feed autotuning and agentic optimization loops that generate, validate, and iteratively optimize kernels and placement decisions based on measured hardware behavior. It concludes with a discussion of future lightweight ML runtimes for heterogeneous embedded systems, emphasizing ahead-of-time model compilation, explicit hardware topology, portable accelerator interfaces, first-class tracing, and closed-loop optimization.
Organizers: Mahesh Madhav, Kunal Kashyap (two current members of SPEC CPU committee)
In May 2026, the latest version of SPEC CPU was released (CPU 2026). As leaders of the committee that crafted this benchmark suite, we want to provide a “behind the scenes” look at the process. We will share how applications were adapted into candidate benchmarks, and how the candidates were culled to create the final benchmark suite. We will share details on why certain classes of applications were excluded, and what that means. We will include a tutorial on recurrence plots for basic-block-vectors, which are a visual aid for determining code self-similarity within a benchmark, one of the inputs for benchmark selection. We will also touch upon the new heterogeneous schedule called rolling round-robin (RRR). There are more multithreaded benchmarks than ever before, so we will share early learnings from MT analysis of the Speed benchmarks, plus other system level sensitivity analysis taken from many-core machines. If there is an opportunity we can discuss the adaptation fidelity of the SPEC CPU benchmarks, that is, how close do the benchmarks represent their original applications. We will end with how the community can continue to support and influence SPEC CPU.
Coffee Break
Program TBD
Program TBD