ADVANCE PROGRAM

Day 1 - Wednesday, October 25, 2006

• Workshop and Tutorials

Day 2 - Thursday, October 26, 2006

  8:30    Opening Remarks

  8:35 – 9:30    Keynote : Luiz Barroso, Google

      ·        Warehouse-sized Workloads

  9:30 – 10:30    Session 1: Characterization of Multimedia and Games Workload         

      ·        Workload Characterization of a Parallel Video Mining Application on a 16-Way Shared-Memory Multiprocessor System  [slide]

     Wenlong Li, Eric Li, Carole Dulong, Yen-Kuang Chen, Tao Wang, Yimin Zhang, Intel Microprocessor Technology Lab

·        Workload Characterization of 3D Games  [slide]

      Jordi Roca, Victor Moya Del Barrio, Carlos González, Chema Solís, Agustín Fernández, Universitat Politécnica de Catalunya, Roger Espasa, Intel DEG Barcelona  

  10:30 - 11:00     Break  

  11:00 - 12:00    Session 2: Energy and Power Behavior of Applications

·         Techniques for Real-System Characterization of Java Virtual Machine Energy and Power Behavior   [slide]

Gilberto Contreras, Margaret Martonosi, Princeton University

·         Application-Aware Power Management   [slide]

Karthick Rajamani, IBM Austin Research Lab, Heather Hanson, University of Texas at Austin, Juan Rubio, Soraya Ghiasi, Freeman Rawson, IBM Austin Research Lab

12:00 - 1:30    Lunch  

  1:30 - 3:00    Session 3: Characterization and Analysis of Bioinformatics Workload 

      ·         Performance Analysis of Sequence Alignment Applications  

Friman Sánchez, Esther Salamí, Alex Ramirez, Mateo Valero, Universitat Politécnica de Catalunya

·         An Architectural Characterization Study of Data Mining and Bioinformatics Workloads    [slide]

      Berkin Ozisikyilmaz, Ramanathan Narayanan, Northwestern University, Joseph Zambreno, Iowa State University, Gokhan Memik, Alok Choudhary, Northwestern University 

·         Load Instruction Characterization and Acceleration of the BioPerf Programs    [slide]

Paruj Ratanaworabhan, Martin Burtscher, Cornell University  

3:00 - 3:30     Break           

  3:30 - 5:00    Session 4: Benchmark Construction and Evaluation

·         Comparing Benchmarks using Key Microarchitecture-Independent Characteristics   [slide]

Kenneth Hoste, Lieven Eeckhout, Ghent University, Belgium

·         Evaluating Benchmark Subsetting Approaches    [slide]

Joshua Yi, Freescale Semiconductor, Resit Sendag, University of Rhode Island, Lieven Eeckhout, Ghent University, Belgium, Ajay Joshi, University of Texas at Austin, David Lilja, University of Minnesota, Lizy John, University of Texas at Austin

·         Performance Cloning : A Technique for Disseminating Proprietary Applications as Benchmarks    [slide]

Ajay Joshi, University of Texas at Austin, Lieven Eeckhout, Ghent University, Belgium, Rob Bell, IBM Austin, Lizy John, University of Texas at Austin

Day 3 - Friday, October 27, 2006

   8:30 - 9:30    Special session on SPEC 2006

      ·         Evolve or die: Making SPEC’s CPU Suite Relevant Today and Tomorrow    [slide]

            Invited Speaker: Jeff Reilly, Intel Corporation, SPEC CPU Committee Chair

      ·         Performance Characterization of SPEC CPU2006 Integer Benchmarks on x86-64 Architecture    [slide]

Dong Ye, Northeastern University, Joydeep Ray, Christophe Harle, AMD, David Kaeli, Northeastern University

  9:30 - 10:00     Break

  10:00 - 12:00    Session 5: Novel Insights and Techniques                         

      ·   The Dynamics of Backfilling: Solving the Mystery of Why Increased Inaccuracy May Help    [slide]

Dan Tsafrir, IBM Watson Research Center, Dror Feitelson, Hebrew University of Jerusalem

•  Characterization of Error-Tolerant Applications when Protecting Control Data   [slide]

Darshan Thaker, University of California, Davis, Diana Franklin, California Polytechnic State University, John Oliver, University of California, Davis, Susmit Biswas, University of California, Santa Barbara, Derek Lockhart, California Polytechnic State University, Tzvetan Metodi, University of California, Davis, Frederic Chong, University of California, Santa Barbara

      ·   Constructing a Non-Linear Model with Neural Networks for Workload Characterization  [slide]

Richard Yoo, Georgia Institute of Technology, Han Lee, Kingsum Chow, Intel Corporation, Hsien-Hsin Lee, Georgia Institute of Technology

•  Modeling Cache Sharing on Chip Multiprocessor Architectures   [slide]

Pavlos Petoumenos, Georgios Keramidas, University of Patras, Greece, Håkan Zeffer, Uppsala University, Sweden, Stefanos Kaxiras, University of Patras, Greece, Erik Hagersten, Uppsala University, Sweden

12:00 - 1:15     Lunch

  1:15 -  2:30    Special Session: New Benchmarks Session

·         DFS: A Simple to Write Yet Difficult to Execute Benchmark    [slide]

Richard Murphy, Bruce Hendrickson, Jonathan Berry, William McLendon, Sandia National Labs, Douglas Gregor, Andrew Lumsdaine, Indiana University

·         Clustering Application Benchmark    [slide]

Oguz Altun, Yildiz Technical University,  Nilgun Dursunoglu, Garanti Teknoloji, Mehmet Fatih Amasyali, Yildiz Technical University,

·         MineBench: A Benchmark Suite for Data Mining Workloads    [slide]

Ramanathan Narayanan, Berkin Ozisikyilmaz, Joseph Zambreno, Gokhan Memik, Alok Choudhary, Northwestern University

  2:30 - 3:00     Break

  3:00 - 4:00    Session 6: Understanding Java Workload

·         Exploring Small-Scale and Large-Scale CMP Architectures for Commercial Java Servers    [slide]

Ravi Iyer, Mahesh Bhat, Li Zhao, Ramesh Illikkal, Srihari Makineni, Michael Jones, Kumar Shiv, Donald Newell, Intel Corporation

·         A Quantitative Evaluation of the Contribution of Native Code to Java Workloads    [slide]

Walter Binder, Jarle Hulaas, Philippe Moret, EPFL, Switzerland

  4:00 - 5:00    Session 7: High Performance Computing Workload   

·         Predicting Bounds on Queuing Delay in Space-shared Computing Environments   [slide]

John Brevik, Daniel Nurmi, Rich Wolski, University of California, Santa Barbara

·         Characterization of Scientific Workloads on Systems with Multi-core Processors   

Sadaf Alam, Richard Barrett, Jeffery Kuehn, Phillip Roth, Jeffrey Vetter, Oak Ridge National Laboratory

  Keynote

"Warehouse-sized Workloads", Luiz Barroso, Google

   Abstract:         

Bio:  Dr. Luiz André Barroso is a Distinguished Engineer at Google, where he has worked across several engineering areas, ranging from applications to software infrastructure and hardware design. His projects have included a service to find related academic articles, designing load-balancing server software, fault detection and recovery techniques, RPC-level networking and server performance optimizations, and leading the design of Google's computing platform.
    Prior to Google he was a member of the Research Staff at Compaq and Digital Equipment Corporations, where his group published extensively on processor and memory system design for database and web server workloads. While at Compaq, he also co-architected and designed Piranha, a scalable shared-memory multiprocessor based on single-chip multiprocessing. Their work on Piranha has had a significant impact in the microprocessor industry, helping inspire many of the multi-core CPUs that are now in the mainstream.
    Before joining Digital he was one of the designers of the USC RPM, an FPGA-based multiprocessor emulator for rapid hardware prototyping. He has also worked at IBM Brazil's Rio Scientific Center and lectured at PUC-Rio (Brazil) and Stanford University.

  Invited talk

      "Evolve or die: Making SPEC’s CPU Suite Relevant Today and Tomorrow", Jeff Reilly, Intel Corporation, SPEC CPU Committee Chair       

   Abstract:        

Bio: Jeff Reilly is a Principal Engineer for Intel Corporation. For the past 16+ years, he has been involved in many aspects of computer benchmarking (development, measurement, analysis, projection), including working with several industry consortiums. In particular, Mr. Reilly has chaired the SPEC CPU Subcommittee for close to 15 years, enjoying the opportunity to work with many talented people in shepherding SPEC’s CPU suite through development, including the recently announced CPU2006.