WWC-7: IEEE 7th Annual Workshop on Workload Characterization

Sponsored by IEEE and the Technical Committee on Computer Architecture

October 25, 2004

Renaissance Hotel Austin, Texas 78759, USA

7:30 AM - 8:30 AMBreakfast

8:30 AM - 9:45 AMSession 1: Memory and Dataflow Characterization
Chair: Ravi Bhargava, AMD

Characterizing the Impact of Different Memory Intensity Levels
Ramakrishna Kotla (University of Texas, Austin), Anirudh Devgan, Soraya Ghiasi, Tom Keller, and Freeman Rawson (IBM Corporation) slide
On the Extraction and Analysis of Prevalent Dataflow Patterns
Peter G. Sassone, and D. Scott Wills (Georgia Institute of Technology) slide
Evaluation of a Speculative Multithreading Compiler by Characterizing Program Dependences
Anasua Bhowmik (Indian Institute of Science), and Manoj Franklin (University of Maryland) slide
9:45 AM - 10:10 AMMid Morning Break

10:10 AM - 11:00 AMSession 2: Media and Network
Chair: Mauricio Breternitz, Intel

GENIUS: Generator of Interactive User media Sessions
Cristiano de Paula Costa, Italo Fernando Scota Cunha, Claudiney Vander Ramos, Jussara Marques de Almeida (Federal University of Minas Gerais) slide
Micro-architectural Anatomy of a Commercial TCP/IP Stack
Ramesh Illikkal, Ravi Iyer,and Don Newell (Intel Corporation) slide
11:00 AM - 12:00 PMKeynote

"TeraFlops for Masses: Killer Apps of Tomorrow"
Pradeep K. Dubey, Intel Corporation
12:00 PM - 1:15 PMLunch

1:15 PM - 2:30PMSession 3: Benchmark Subsetting, Tracing and Workload Generation
Chair: Nasr Ullah, Freescale

Does Halting Make Hardware Trace Collection Inaccurate? A Case Study Using Pentium 4 Performance Counters and SPEC2000
Myles G. Watson, and J. Kelly Flanagan (Brigham Young University)
Experiments with Subsetting Benchmark Suites
Hans Vandierendonck, and Koen De Bosschere (Ghent University) slide
The USAR Characterization Model
Adriano Pereira (Smart Price Research Center), Gustavo Franco, Leonardo Silva, Wagner Meira Jr., and Walter Santos (Federal University of Minas Gerais) slide
2:30 PM - 3:00 PMMid Afternoon Break

3:00 PM - 3:50 PMSession 4: High Performance Computing
Chair: Alex Mericas, IBM

Construction and Performance Characterization of Parallel Interior Point Solver on 4-way Intel Itanium Multiprocessor System
Pranay Koka (University of Wisconsin), Taeweon Suh (Georgia Institute of Technology) , Radek Grzeszczuk, Mikhail Smelyanskiy, Carole Dulong (Intel Corporation) slide
Performance Characterization of BLAST on Intel Xeon and Itanium2 Processors
Ramesh Radhakrishnan, Rizwan Ali, Garmia Kochhar, Kalyan Chadalavada, Ramesh Rajagopalan, Jenwei Hsieh, Onur Celebioglu (Dell Corporation) slide
3:50 PM - 4:00 PMPanel Preparation

4:00 PM - 5:15 PMPanel Discussion   pictures

Moderator: Marc McDermott, The University of Texas at Austin

"Challenges in Capturing Real World Workloads into Benchmarks"
Users want benchmarking results that closely correlate with actual performance of real world workloads. SPEC and other benchmarking consortiums try to capture real-world workloads. However, benchmarking continues to be a challenge. Speakers from SPEC, IBM, Intel, academic researchers and computer users look into the challenges of capturing real world workloads into benchmarks.
  • Kaivalya Dixit (SPEC and IBM) slide
  • David Lilja (Minnesota) slide
  • Jeff Reilly (SPEC and Intel) slide
  • David Williamson (ARM) slide

Keynote Speech

Title: "TeraFlops for Masses: Killer Apps of Tomorrow"

Speaker: Pradeep K. Dubey, Intel Corporation


Many think that the general-purpose processors we use today have enough power to run most applications. This is what we call 'good enough computing.' And many believe that the design complexity and power limitations of modern-day processors don't allow them to scale well to next levels of performance. If all this is true, perhaps we have reached the supply-demand equilibrium, which says, "We cannot offer significant speedup of your apps, and why do you need it anyway?" This talk is about why this is a myth. Next generation general-purpose mass applications require processing power of TeraFlops and beyond, and resulting workloads are likely to have profound implications for processor platform designs of tomorrow.

Pradeep Dubey


Dr. Pradeep K. Dubey is a senior principal engineer and manager of innovative platform architecture in the Corporate Technology Group at Intel.

His research interests include computer architectures for new application paradigms in future computing environments. Dubey previously worked at the IBM T.J. Watson Research Center and at Broadcom. He was one of the principal architects for the AltiVec multimedia extension to the PowerPC architecture.

He also worked on the design, architecture, and performance issues of various microprocessors, including Intel's 80386, 80486, and Pentium processors. He holds 24 patents and is an IEEE Fellow.