IISWC 2018 Program

IISWC-2018

September 30 - October 2, 2018

Raleigh, North Carolina, USA

Program

Day 1, Sep 30th

8:00-8:45	Breakfast
8:45-12:00	Tutorial 1 Infrastructure and Methodology for SoC Performance and Power Modeling
10:15-10:45	Coffee Break
12:00-1:30	Lunch (on your own)
1:30-5:00	Tutorial 2 Integrated Algorithm and System Solutions for Deep Learning Acceleration
3:00-3:30	Coffee Break

Day 2, Oct 1st

8:00-8:45	Breakfast
8:45-9:00	Opening & Welcome
9:00-10:00	Keynote Address I by Dr. Vijayalakshmi Srinivasan, IBM
10:00-10:15	Coffee Break
10:15-11:45	Session 1: Benchmark Formation and Suites
11:45-1:15	Lunch
1:15-2:45	Session 2: Systems and Software
2:45-3:00	Coffee Break
3:00-4:00	Session 3: Hot Workloads Special Session
4:15-5:45	Session 4: Poster Presentation

Day 3, Oct 2nd

8:00-9:00	Breakfast and Opening
9:00-10:00	Keynote Address II by Dr. Christopher Hughes, Intel
10:00-10:15	Coffee Break
10:15-12:15	Session 5: Machine Learning
12:15-1:30	Lunch Keynote Address III by Dr. Cliff Young, Google
1:30-3:00	Session 6: Memory and Storage
3:00-3:15	Coffee Break
3:15-5:15	Session 7: Best Paper
5:15-5:30	Closing

Program Details

**Day 1, Sep 30th**
8:00-8:45	Breakfast Room: Synergy Ballroom A
8:45-12:00	Tutorial 1 (Morning) Infrastructure and Methodology for SoC Performance and Power Modeling Organizers: Yuhao Zhu, University of Rochester Jeffrey Liao, Synopsys AI Lab Abstract: Mobile systems are increasing integrating domain-specific accelerators and IP blocks. Analysis of die photos from three generations of Apple’s SoCs: A6 (iPhone 5), A7 (iPhone 5S) and A8 iPhone 6), shows that consistently more than half of the die area is dedicated to blocks that are neither CPUs nor GPUs, most of which are application-specific hardware accelerators. Therefore, computer architectures must now expand the research scope from optimizing individual IP blocks in isolation to consider the entire SoC as a whole. The main objective of our tutorial is to foster SoC-level computer architecture research whose major barrier of entry now is a lack of basic tools and infrastructures. Other areas in computer architecture such as GPU and data-centers have mature infrastructures such as simulators and workload suites that have been developed for years and are now widely adopted. Although the nature of SoC research emphasizes on real system modeling and measurements, we currently lack systematic infrastructures that are easily accessible and widely adopted. The tutorial is a step to mitigate this gap in the community. The tutorial is meant for researcher, students, and practitioners in the field who are interested in conducting architectural research at the scale of System-on-a-chip (SoC). Audience is not expected to have any prior knowledge of SoC and SoC-level modeling, but is expected to have preliminary knowledge of basic computer architecture. Room: Synergy Ballroom A
10:15-10:45	Coffee Break Room: Synergy Ballroom A
12:00-1:30	Lunch (on your own)
1:30-5:00	Tutorial 2 (Afternoon) Integrated Algorithm and System Solutions for Deep Learning Acceleration Organizers: Hai Li, Duke University Abstract: With the rapid advances in deep neural networks (DNNs), the effectiveness in hardware implementation emerges as an important concern. In practical use, both testing (inference) phase and sophisticated training (learning) phase are required, calling for efficient testing and training methods with higher accuracy and shorter converging time. The challenge requires integrated solutions cross algorithm and system levels, which will be the focus of this tutorial. The talk will start with the DNN history. We then will present some representative techniques for improving computation, communication and storage efficiency. The optimization on distributed systems will also be discussed. Room: Synergy Ballroom A
3:00-3:30	Coffee Break Room: Synergy Ballroom A

**Day 2, Oct 1st**
8:00-8:45	Breakfast Room: Synergy Ballroom A
8:45-9:00	Opening & Welcome Room: Synergy Ballroom A
9:00-10:00	Keynote Address I: Across the Stack Approximate Computing Opportunities for Deep Learning Acceleration Dr. Vijayalakshmi Srinivasan, IBM Session Chair: Drew Hilton Room: Synergy Ballroom A
10:00-10:15	Coffee Break Room: Synergy Ballroom A
10:15-11:45	Session 1: Benchmark Formation and Suites Session Chair: David Kaeli Room: Synergy Ballroom A
10:15-11:45	µSuite: A Benchmark Suite for Microservices Akshitha Sriraman (University of Michigan), Thomas F. Wenisch (University of Michigan) AutomataZoo: A Modern Automata Processing Benchmark Suite Jack Wadden (University of Virginia), Tommy Tracy II (University of Virginia), Elaheh Sadredini (University of Virginia), Lingxi Wu (University of Virginia), Chunkun Bo (University of Virginia), Jesse Du (University of Virginia), Yizhou Wei (University of Virginia), Matthew Wallace (University of Virginia), Jeffrey Udall (University of Virginia), Mircea Stan (University of Virginia), Kevin Skadron (University of Virginia) VComputeBench: A Vulkan Benchmark Suite for GPGPU on Mobile and Embedded GPUs Nadjib Mammeri (Technische Universitat Berlin), Ben Juurlink (Technische Universitat Berlin)
11:45-1:15	Lunch Room: Synergy Ballroom B
1:15-2:45	Session 2: Systems and Software Session Chair: Hung-Wei Tseng Room: Synergy Ballroom A
1:15-2:45	Quantitative Overhead Analysis for Python Mohamed Ismail (Cornell University), G. Edward Suh (Cornell University) Data Motif-based Proxy Benchmarks for Big Data and AI Workloads Wanling Gao (ICT, CAS), Jianfeng Zhan (ICT, CAS), Lei Wang (ICT, CAS), Chunjie Luo (ICT, CAS) Zhen Jia (Princeton University), Daoyi Zheng (ICT, CAS), Chen Zheng (ICT, CAS), Xiwen He (ICT, CAS), Hainan Ye (Beijing Academy of Frontier Sciences and Technology), Haibin Wang (Huawei), Rui Ren (ICT, CAS) A NUMA-aware provably-efficient task parallel platform based on the work-first principle Justin Deter (Washington University in St. Louis), Jiaye Wu (Washington University in St. Louis), Yifan Xu (Washington University in St. Louis), I-Ting Angelina Lee (Washington University in St. Louis)
2:45-3:00	Coffee Break Room: Synergy Ballroom A
3:00-4:30	Session 3:Hot Workloads Special Session Session Chair: Drew Hilton Room: Synergy Ballroom A
3:00-4:30	Invited Talk 1: On the Performance Cost of Secure Execution Environment Yan Solihin, University of Central Florida Invited Talk 2: Hot Regions in Hot Workloads Lizy John, UT-Austin Invited Talk 3: The Modern Enterprise Data Center -- Changes are Afoot Josh Simons, VMware
4:30-6:00	Session 4: Poster Session Room: The Hub
4:30-6:00	ParchMint: A Microfluidics Benchmark Suite Brian Crites (University of California, Riverside), Radhakrishna Sanka (Boston University), Joshua Lippai (Boston University), Jeffrey McDaniel (University of California, Riverside), Douglas Densmore (Boston University), Philip Brisk (University of California, Riverside) ChopStiX: Systematic Extraction of Code-Representative Microbenchmarks Calvin Bulla (BSC), Miquel Moreto (BSC), Lluc Alvarez (BSC), Ramon Bertran (IBM), Alper Buyuktosunoglu (IBM), Pradip Bose (IBM) Characterizing DNN Models for Edge-cloud Computing Chunwei Xia (University of Chinese Academy of Sciences), Jiacheng Zhao (University of Chinese Academy of Sciences), Huimin Cui (University of Chinese Academy of Sciences), Xiaobing Feng (University of Chinese Academy of Sciences) Gene Sequencing: Where Time Goes Meysam Roodi (University of Toronto), Andreas Moshovos (University of Toronto) Characterizing Sources of Ineffectual Computations in Deep Learning Networks Milos Nikolic (University of Toronto), Mostafa Mahmoud (University of Toronto), Andreas Moshovos (University of Toronto)

**Day 3, Oct 2nd**
8:00-9:00	Breakfast and Opening Room:
9:00-10:00	Keynote Address II: Irregular Parallel Workloads on General-Purpose Processors Dr. Christopher Hughes, Intel Session Chair: Carole-Jean Wu Room: Synergy Ballroom A
10:00-10:15	Coffee Break Room: Synergy Ballroom A
10:15-12:15	Session 5: Machine Learning Session Chair: Amrit Panda Room: Synergy Ballroom A
10:15-12:15	Benchmarking and Analyzing Deep Neural Network Training Hongyu Zhu (University of Toronto), Amar Phanishayee (Microsoft Research), Gennady Pekhimenko (University of Toronto), Bianca Schroeder (University of Toronto), Bojian Zheng (University of Toronto), Mohamed Akrout (University of Toronto), Andrew Pelegris (University of Toronto), Anand Jayarajan (University of British Columbia) Characterising Across-Stack Optimisations for Deep Convolutional Neural Networks Jack Turner (University of Edinburgh), Jose Cano (University of Edinburgh), Valentin Radu (University of Edinburgh), Elliot J. Crowley (University of Edinburgh), Michael O'Boyle (University of Edinburgh), Amos Storkey (University of Edinburgh) Memory Requirements for Convolutional Neural Network Hardware Accelerators Kevin Siu (University of Toronto), Dylan Malone Stuart (University of Toronto), Mostafa Mahmoud (University of Toronto), Andreas Moshovos (University of Toronto) Profiling DNN Workloads on a Volta-based DGX-1 System Saiful A. Mojumder (Department of Electrical and Computer Engineering, Boston University), Marcia S Louis (Department of Electrical and Computer Engineering, Boston University), Yifan Sun(Electrical and Computer Engineering Dept., Northeastern University), Amir Kavyan Ziabari (Advanced Micro Devices), Jose L. Abellan (Computer Science Dept., Universidad Catolica San Antonio de Murcia) John Kim (Department of Computer Science, KAIST), David Kaeli (Electrical and Computer Engineering Dept., Northeastern University), Ajay Joshi (Department of Electrical and Computer Engineering, Boston University)
12:15-1:30	Lunch Keynote III: MLPerf: Fair and Useful Benchmarks for Machine-Learning Systems Dr. Cliff Young, Google Session Chair: Brian Rogers Room: Viewpoint
1:30-3:00	Session 6: Memory and Storage Session Chair: Brandon Reagen Room: Synergy Ballroom A
1:30-3:00	Heterogeneous Memory Subsystem for Natural Graph Analytics Abraham Addisie (University of Michigan), Hiwot Kassa (University of Michigan), Luwa Matthews (University of Michigan), Valeria Bertacco (University of Michigan) Minimizing Read Seeks for SMR Disk Mohammad Hossein Hajkazemi (Northeastern University), Mania Abdi (Northeastern University), Peter Desnoyers (Northeastern University) Reviving Zombie Pages on SSDs Nima Elyasi (The Pennsylvania State University), Anand Sivasubramaniam (The Pennsylvania State University), Mahmut T. Kandemir (The Pennsylvania State University), Chita R. Das (The Pennsylvania State University)
3:00-3:15	Coffee Break Room: Synergy Ballroom A
3:15-5:15	Session 7: Best Paper Session Chair: Kelly Shaw Room: Synergy Ballroom A
3:15-5:15	Simulating PCI-Express Interconnect for Future System Exploration Mohammad Alian(UIUC), Krishna Parasuram Srinivasan (UIUC), Nam Sung Kim (UIUC) Interference from GPU System Service Requests Arkaprava Basu (Indian Institute of Science), Joseph L. Greathouse (Advanced Micro Devices Inc.), Guru Venkataramani, (George Washington University), Jan Vesely (Rutgers University) Tartan: Evaluating Modern GPU Interconnect via a Multi-GPU Benchmark Suite Ang Li (Pacific Northwest National Laboratory), Shuaiwen Leon Song (Pacific Northwest National Laboratory), Jieyang Chen (Pacific Northwest National Laboratory), Xu Liu (College of William & Mary), Nathan Tallent (Pacific Northwest National Laboratory), Kevin Barker (Pacific Northwest National Laboratory) When is Graph Reordering an Optimization? Studying the Effect of Lightweight Graph Reordering Across Applications and Input Graphs Vignesh Balaji (CMU), Brandon Lucia (CMU)
5:30-5:45	Closing