IISWC-2013

September 22-24, 2013

 Portland, Oregon, USA
 

TUTORIAL SCHEDULE

  Tutorials will be held at Skyline II Lounge on September 22, 2013.

 


TUTORIAL DESCRIPTIONS

Tutorial I: The Sniper Multi-Core Simulator

Two major trends in high-performance computing, namely, larger numbers of cores and the growing size of on-chip cache memory, are creating significant challenges for evaluating the design space of future processor architectures. Fast, scalable and accurate simulations are needed to allow for sufficient exploration of large multi-core systems within a limited simulation time budget. Through the use of high-abstraction analytical models with fast parallel simulation in the Sniper simulator, computer architects can trade off accuracy with simulation speed to allow for longer application runs, covering a larger portion of the hardware design space.

The purpose of this tutorial is to introduce both the main features of the Sniper simulator, as well as provide detail into the use of the simulator itself. Specifically, this tutorial will provide an in-depth look into the theory and implementation of the interval core model and CPI-stack generation. We will give a detailed rundown of how to specify heterogeneous architectures and implement scheduling algorithms. We also highlight other features such as full DVFS support, scripting and program-to-simulator communication and provide an overview of the various component models and simulator configurability and flexibility.

More details on this tutorial is available here. 

Tutorial II: Modeling Exascale Applications with SST/macro and Eiger

In high performance computing (HPC), the importance of fast, large scale models of high ?delity are only increasing
as we move towards the next frontier of exascale. Hardware/software codesign is viewed as a key methodology
to reaching this end. The SST/macro toolkit provides HPC engineers the ability to explore current and future
hardware/software design constraints. Instead of costly (in time and user e?ort) cycle-accurate simulation, macro-
scale simulation can provide valuable insight into the performance of large applications. The value of these tools lies
in high quality application models for increasingly complex hardware designs.

The Eiger Performance Modeling Framework generates models by applying statistical techniques from the ?eld
of machine learning on empirical performance data. While macro-scale simulation can provide a reasonable overview
of system wide phenomena, Eiger can leverage data acquired from micro-scale sources to inform large scale simulations
in SST/macro. Eiger provides an API and data store for aggregating data from micro-scale sources such as simulators,
emulators, and runtime instrumentation.

This tutorial will present attendees with the techniques and methodologies to leverage SST/macro and Eiger
for modelling large scale applications on upcoming supercomputer hardware. This presentation is geared towards
domain experts and HPC hardware designers, as well as students and researchers whose work requires exploration of
programming models, interaction between computation and communication, and data-driven modelling techniques for
large scale systems. These tools are geared toward ease of use and rapid iteration, allowing area experts to generate
verbose performance models without requiring intricate knowledge of every facet of the computing environment. This
tutorial will require only a basic level of programming skill.

More details on this tutorial is available here. 

Tutorial III: Genomics and Towards Personalized Medicine

This tutorial will provide an introduction to the field of computation genomics, focusing on the SW tools used to perform DNA/RNA sequencing as well as advanced analysis targeted towards personalized medicine.

More details on this tutorial is available here.