IISWC-2007

September 27-29 2007

Four Point Sheraton Logan Airport

Boston, MA, USA

 

 

CONFERENCE PROGRAM

 



Tech Sessions: Thursday, September 27 | Friday, September 28
Thursday, September 27
8:00 a.m.–8:30 a.m. Thursday
Breakfast and Registration

8:30 a.m.–8:45 a.m. Thursday
Welcome Remarks

8:45 a.m.–9:45 a.m. Thursday
Keynote Speech I
The SPEC Gorilla Turns One. So What?
John Henning, Sun Microsystems

SPEC CPU2006 is a 500 pound gorilla of benchmarking, with 1300 results published since its release one year ago (24 August 2006), despite consuming vastly more time and computational resources than its predecessor suites.

What have we learned about its workloads during its first year of life? Are there surprises lurking in the code, workloads, or run rules that are difficult to simulate? What characteristics of CPU2006 have proven successful? What does SPEC need to improve in successor suites? Some proposed answers will be provided and time will be reserved for an open microphone. The presenter will also be available during breaks to listen to feedback about the suite.

A collection of eleven technical articles about SPEC CPU2006 will be given away; sit near the front of the room to improve your chances of receiving a hard copy.

John L. Henning is a Performance Engineer at Sun Microsystems and is Secretary for the SPEC CPU Subcommittee. He has contributed to performance analysis and improvement of software on PDP-11, VAX, Alpha, and SPARC systems, including, in 1980, an implementation of a client/server text processing workload based on observed user workloads. His first successful performance project was shrinking a SORT process on an IBM 360/30 from 8 hours to 20 minutes. This speedup was accomplished by improving the match between the user requirements, the available computational resources, and the workload.

9:45 a.m.–10:15 a.m.    Break

10:15 a.m.–12:15 p.m. Thursday
Predicting and Implications on Application Performance
Session Chair: Aamer Jaleel, Intel

Characterizing the Effect of Microarchitecture Design Parameters on Workload Dynamic Behavior
Chang-Burm Cho, Wangyuan Zhang, Tao Li, University of Florida

Implications of Conflict Rate Trends for Robust Software Transactional Memory
Craig Zilles, University of Illinois at Urbana-Champaign; Ravi Rajwar, Intel Corporation

Predicting Program Behavior Based On Objective Function Minimization
Ruhi Sarikaya, Alper Buyuktosunoglu, IBM Research

On the Effects of Memory Latency and Bandwidth on Supercomputer Application Performance
Richard C. Murphy, Sandia National Laboratories

12:15 p.m.–1:30 p.m.    Lunch

1:30 p.m.–3:00 p.m. Thursday
Multi-core
Session Chair: Bhuvan Urgaonkar, Penn State University

Evaluation of Server Consolidation Workloads for Multi-core Designs
Natalie Enright Jerger, Dana Vantrease, Mikko H. Lipasti, University of Wisconsin - Madison

Performance Studies of Commercial Workloads on a Multi-core System
Jessica H. Tseng, Hao Yu, Shailabh Nagar, Niteesh Dubey, Hubertus Franke, Pratap Pattnaik, Hiroshi Inoue, Toshio Nakatani, IBM Research

Addressing Cache/Memory Overheads in Enterprise Java CMP Servers
Kumar Shiv, Mahesh Bhat, Mike Jones, Ramesh Illikal, Srihari Makineni, Don Newell, Jason Domer, Ravi Iyer, Intel

3:00 p.m.–3:30 p.m.    Break

3:30 p.m.–4:30 p.m. Thursday
Benchmark Studies
Session Chair: John Henning, Sun Microsystems

Benchmarking BGP Routers
Qiang Wu, Yong Liao, Tilman Wolf, Lixin Gao, University of Massachusetts

Characterizing and Improving the Performance of Bioinformatics Workloads on the POWER5 Architecture
Vipin Sachdeva, Evan Speight, Mark W. Stephenson, IBM Research; Lei Chen, IBM Systems and Technology Group

4:45 p.m. - 6:00 p.m. Thursday
Panel Session
Benchmarking in the Web 2.0 Era
Moderator: Sudhanva Gurumurthi, University of Virginia, Slides
Panelists:
  • Randal Bryant, Carnegie Mellon University, Slides
  • Shubhendu Mukherjee, Intel Corporation, Slides
  • Suchi Raman, Netezza Corporation, Slides
  • Prashant Shenoy, University of Massachusetts, Slides
  • Akara Sucharitakul, Sun Microsystems, Slides
    • Friday, September 28
    8:00 a.m.–8:45 a.m. Friday
    Breakfast

    8:45 a.m.–9:45 a.m. Friday
    Keynote Speech II
    Taking Concurrency Seriously: the Multicore Challenge
    Maurice Herlihy, Brown University

    Computer architecture is undergoing, if not another revolution, then a vigorous shaking-up. The major chip manufacturers have, for the time being, simply given up trying to make processors run faster. Instead, they have recently started shipping "multicore'' architectures, in which multiple processors (cores) communicate directly through shared hardware caches, providing increased concurrency instead of increased clock speed. As a result, system designers and software engineers can no longer rely on increasing clock speed to hide software bloat. Instead, they must somehow learn to make effective use of increasing parallelism. This adaptation will not be easy. Conventional synchronization techniques based on locks and conditions are unlikely to be effective in such a demanding environment.

    Transactional memory is a computational model in which threads synchronize by transactions. This synchronization model promises to alleviate many (perhaps not all) of the problems associated with locking, and there is a growing community of researchers working on both software and hardware support for this approach. This talk will survey the area, with a focus on open research problems.

    Maurice Herlihy has an A.B. in Mathematics from Harvard University and a Ph.D. in Computer Science from MIT. He has been an Assistant Professor in the Computer Science Department at Carnegie Mellon, a member of research staff at Digital Equipment Corporation's Cambridge (MA) Research Lab, and a consultant for Sun Microsystems. He is now a Professor of Computer Science at Brown University. His 1991 paper "Wait-Free Synchronization" won the 2003 Dijkstra Prize in Distributed Computing, and he shared the 2004 Goedel Prize for his 1999 paper "The Topological Structure of Asynchronous Computation." He is a Fellow of the ACM.

    9:45 a.m.–10:15 a.m.    Break

    10:15 a.m.–11:45 a.m. Friday
    Benchmarks
    Session Chair: Lieven Eeckhout, Ghent University

    Pynamic: The Python Dynamic Benchmark Behavior
    G. L. Lee, D. H. Ahn, B. R. de Supinski, J. Gyllenhaal, P. Miller, Lawrence Livermore National Laboratory

    Delaunay Triangulation with Transactions and Barriers
    M. L. Scott, M. F. Spear, L. Dalessandro, V. J. Marathe, University of Rochester

    FacePerf: Benchmarks for Face Recognition Algorithms
    D. S. Bolme, M. Strout, J. R. Beveridge, Colorado State University

    HD-VideoBench: A Benchmark for Evaluating High Definition Digital Video
    M. Alvarez, E. Salami, A. Ramirez, M. Valero, UPC and BSC

    11:45 a.m.–1:30 p.m.    Lunch

    1:30 p.m.–3:00 p.m. Friday
    Tracing and Online Characterization
    Session Chair: Robert Cohn, Intel

    Seekable Compressed Traces
    Tip Moseley, Dirk Grunwald, University of Colorado at Boulder; Ramesh Peri, Intel

    Analysis of Statistical Sampling in Microarchitecture Simulation: Metric, Methodology, and Program Characterization
    Sreekumar V. Kodakara, Jinpyo Kim, David J. Lilja, Wei-Chung Hsu, Pen-Chung Yew, University of Minnesota

    Efficient Disk I/O Characterization using Online Histograms in a Virtual Machine Hypervisor
    Irfan Ahmad, VMware

    3:00 p.m.–3:30 p.m.    Break

    3:30 p.m.–4:30 p.m. Friday
    Data Center Applications
    Session Chair: Anton Chernoff, AMD

    An Observation-Based Approach to Performance Characterization of Distributed n-Tier Applications
    Calton Pu, Akhil Sahai, HP Labs; Jason Parekh, Gueyoung Jung, Ji Bae, You-Kyung Cha, Timothy Garcia, Danesh Irani, Jae Lee, Qifeng Lin, Georgia Institute of Technology

    Workload Anaysis and Demand Prediction of Enterprise Data Center Applications
    Daniel Gmach, Technische Universitat Munchen; Jerry Rolia, Ludmila Cherkasova, HP Labs; Alfons Kemper, Technische Universitat Munchen

    4:30 p.m. - 6:00 p.m. Friday
    Compact Workload Creation
    Session Chair: Paul Drongowski, AMD

    SCRAP: A Statistical Approach for Creating Compact Representational Query Workload based on Performance Bottlenecks
    James A. Skarie, Biplob K. Debnath, David J. Lilja, Mohamed F. Mokbel, University of Minnesota

    Representative Multiprogram Workloads for Multithreaded Processor Simulation
    Michael Van Biesbrouck, UCSD; Lieven Eeckhout, Ghent University; Brad Calder, UCSD, Microsoft

    Hierarchical Means: Single Number Benchmarking with Workload Cluster Analysis
    Richard M. Yoo, Hsien-Hsin S. Lee, Georgia Tech.; Han Lee, Kingsum Chow, Intel

     

     

     

     

     

     

     

     

     

     

                            

     

    This Web site is maintained by the IISWC 2007 Committee. Please contact the Web chair (bhuvan @ cse . psu . edu) if you have any questions.